Analog to digital conversion using nonuniform sample rates

ABSTRACT

A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the U.S. National Phase of application Ser. No.PCT/US94/10268, filed Sep. 13, 1994, which in turn is acontinuation-in-part of application Ser. No. 08/121,104, filed Sep. 13,1993, abandoned, entitled ANALOG TO DIGITAL CONVERSION USING NON-UNIFORMSAMPLE RATES.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of methods andcircuits for analog to digital conversion. More particularly, thepresent invention relates to a method and circuit for analog to digitalsignal conversion using sigma-delta modulation of the temporal spacingbetween digital samples.

2. Discussion of the Related Art

Analog to Digital Converter (ADC) circuits and methods for analog todigital conversion are well-known in the art. Conventional ADCs receivean analog signal and, as a function of a reference voltage, convert theanalog signal into a corresponding single or multi-bit binary leveldigital signal.

One type of ADC that has recently become popular is the so-calledsigma-delta ADC. There are many references describing sigma-deltasystems. One example is entitled Mixed-Signal Design Seminar publishedby Analog Devices, Inc., 1991, which is incorporated herein byreference.

As shown in FIG. 1, a conventional sigma-delta analog to digitalconverter includes an analog low-pass filter 1 having a passband fromzero to an upper frequency f_(a). The analog low-pass filter typicallyhas a stop band frequency equal to

kf_(s) /2 where f_(s) is the sample rate

The analog low-pass filter implements a portion of a requiredanti-aliasing function for the ADC. The filtered analog signal is thentransmitted to an analog to digital converter 2 that uses a sigma-deltamodulator to convert the analog signal into a one-bit digital datastream and to noise shape the digital data stream. In A to D converters,the sigma-delta modulators are typically all analog. The sigma-deltamodulator effectively low-pass filters the signal of interest andhigh-pass filters the quantization noise on the signal. The output ofthe sigma-delta modulator is typically a high frequency one-bit datastream. The A to D converter is typically clocked at a frequency kf_(s)that is k times the samples rate (i.e., data rate or samplingfrequency). This produces a so-called oversampled signal. The output ofthe sigma-delta modulator is transmitted to a digital low-pass filter 3that implements the anti-aliasing function with respect to f_(s) and hassufficient stop band attenuation at f_(s) /2 to achieve the desireddynamic range. The digital low-pass filter removes the shapedquantization noise that resides in the upper frequency area. The outputof the digital low-pass filter is transmitted to a decimator 4 thatprovides a data rate reduction to f_(s) by digitally resampling theoutput of the digital low-pass filter. Decimation can also be viewed asthe method by which the redundant information introduced by theoversampling process is removed.

One of the limitations of conventional ADCs including the sigma-deltaADC illustrated in FIG. 1 is that they only determine the magnitude ofthe input signal at equally spaced temporal intervals. This is known asuniform sampling. Additionally, in conventional ADCs, the sample rate,that is, the data rate f_(s), of the digital data stream cannot beindependent of the master clock that is used to clock the ADC. Thedigital data rate f_(s) must be some integer division of the masterclock. This means that if two different output data rates were required,for example, that are not necessarily divisible into the master clock,there must be two different frequency master clocks available forclocking the ADC.

Another problem with conventional ADCs is that they are typically notdesigned to be clocked by an externally supplied clock signal. Thecomponents of the ADC are typically optimized to operate at the clockfrequency determined by the master clock on the ADC chip. This leads tothe additional limitation that some ADCs cannot lock to and operate atsome externally supplied clock signal. Therefore, if the digital datastream is supplied to some other external component that is clocked byanother clock signal, since the outgoing digital data stream and theother clock signal are not necessarily related to each other (or to themaster clock on the ADC), any temporal changes in the relationshipbetween the data rate and the other clock can disrupt the entire analogto digital conversion process.

Therefore, an object of the present invention is to provide a method andapparatus for performing analog to digital conversion using nonuniformsampling (i.e., variable temporal spacing of the sampling points).

Another object of the present invention is to provide a method andapparatus for performing analog to digital conversion that can lock toan externally supplied clock signal and can provide an output signal ata sampling rate that is independent of the ADC master clock.

SUMMARY OF THE INVENTION

The present invention overcomes the limitations of the prior art byproviding a method and apparatus for analog to digital conversion usingnonuniform sampling. In one embodiment of the invention, the apparatusincludes an analog to digital converter for converting an analog signalto a digital signal at a first data rate. An interpolator or othercomparable circuitry such as a sample and hold circuit is coupled to theanalog to digital converter and receives the digital signals at thefirst data rate and supplies the digital signals at an increased datarate. A decimator is coupled to the interpolator and decimates thedigital signals at the increased data rate to provide digital signals ata second data rate. In one embodiment, a sigma-delta modulator iscoupled to and controls the interpolator and provides a sigma-deltamodulated output signal representative of the second data rate tocontrol the interpolator to provide the digital signals at the increaseddata rate so that, upon decimation by the decimator, the digital signalsare at the second data rate. This embodiment of the inventioninterpolates the digital data by a variable ratio depending on thesecond data rate desired and then decimates the interpolated digitaldata by a fixed ratio.

In another embodiment of the invention, the apparatus includes an analogto digital converter for converting an analog signal to a digital signalat a first data rate. An interpolator or other comparable circuitry suchas a sample and hold circuit is coupled to the analog to digitalconverter and receives the digital signal at the first data rate andsupplies the digital signals at an increased data rate. A decimator iscoupled to the interpolator and decimates the digital signal at theincreased data rate to provide digital signals at a second data rate. Asigma-delta modulator is coupled to and controls the decimator andprovides a sigma-delta modulated output signal representative of thesecond data rate and controls the decimator to provide the digitalsignals at the second data rate. The sigma-delta modulator may alsocontrol a clock randomizer/suppressor circuit that in turn controls thedecimator to avoid unwanted tones in the output digital signal. Thisembodiment of the invention interpolates the digital data by a fixedratio and then decimates the interpolated digital data by a variableratio depending on the second data rate desired.

In another embodiment of the invention, a phase locked loop (PLL) whichmay be a digital or analog PLL is provided for receiving a signalrepresentative of the second data rate, locking to the signal, andproviding a control signal to the sigma-delta modulator that controlsthe sigma-delta modulator to provide the sigma-delta modulated outputsignal. The sigma-delta modulator forms part of the digitally controlledoscillator in the PLL. The phase locked loop allows the circuit to lockto and track any externally-supplied clock signal.

Broadly stated, the method of the present invention includes sigma-deltamodulation of the time base such that errors produced by nonumiformsampling are frequency-shaped to a region (i.e., shifted to higherfrequencies) where they can be removed by conventional filteringtechniques. That is, the method of the present invention provides atemporally noise-shaped digital signal.

In one embodiment of the invention, the method is to perform a variableinterpolation (or other method to increase the sample rate of thedigital data stream) and filtering to remove images followed by a fixeddecimation with the interpolation controlled by a sigma-delta modulatorthat is fed a frequency selection number representing the desired outputsample rate. Variable interpolation means that the interpolation ratiois varied as a function of the desired output sample rate. Fixeddecimation means that the decimation ratio is the same regardless of thesample rate. A digital data stream output by an analog to digitalconverter (ADC) at a first data rate is interpolated to a higher datarate using a control signal that is a sigma-delta modulated signal thatrepresents the desired output data rate (or sample rate). The frequencyselection signal is modulated using an n-th order m-bit sigma-deltamodulator. This control signal (the sigma-delta modulated frequencyselection signal output by the sigma-delta modulator) represents, onaverage, the sample rate of the digital data to be output by theconverter. The control signal controls the interpolator to increase thedata rate such that, upon fixed decimation, data emerges from theinterpolation/decimation process at the desired output sample rate.

In another embodiment of the invention, the method is to perform a fixedinterpolation (or other method to increase the sample rate of thedigital data stream) and filtering to remove images followed by avariable decimation with the decimation controlled by a sigma-deltamodulator that is fed a frequency selection number representing thedesired sample rate of the output digital data stream. Fixedinterpolation means that the interpolation ratio is the same regardlessof the sample rate. Variable decimation means that the decimation ratiois varied as a function of the desired output sample rate. A digitaldata stream output by an analog to digital converter (ADC) at a datarate is interpolated to a higher data rate. This higher data ratedigital data stream is then decimated using a control signal that is asigma-delta modulated signal that represents the desired output datarate (or sample rate). The frequency selection signal is modulated usingan n-th order m-bit sigma-delta modulator. This control signal (thesigma-delta modulated frequency selection signal output by thesigma-delta modulator) represents, on average, the sample rate of thedigital data to be output by the converter. Data thus emerges from theinterpolation/decimation process at the desired output sample rate.

The method thus converts the data rate of the digital data stream outputby the analog to digital converter from an oversampled signal to adigital data stream having the desired sample rate.

The features and advantages of the present invention will be morereadily understood and apparent from the following detailed descriptionof the invention, which should be read in conjunction with theaccompanying drawings, and from the claims which are appended at the endof the detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are incorporated herein by reference and in whichlike elements have been given like reference characters,

FIG. 1 is a block diagram of a conventional sigma-delta analog todigital converter (ADC);

FIG. 2 is a block diagram of a general ADC circuit incorporating a firstembodiment of the invention;

FIG. 3 is a more detailed block diagram of a sigma-delta ADC circuitincorporating the first embodiment of the invention;

FIG. 4 is a block diagram of a circuit for supplying previously storedfrequency numbers to the n-th order m-bit sigma-delta modulator of FIGS.2-3, and FIGS. 7-8, and FIG. 10;

FIG. 5 is a block diagram of a locking circuit that may be used inconjunction with the circuits of FIGS. 2-3, FIGS. 7-8, and FIG. 10 tolock the ADC to an externally supplied clock signal; and

FIG. 6 is a flow chart illustrating the steps of the method of theinvention using variable interpolation followed by fixed decimation.

FIG. 7 is a block diagram of a general ADC circuit incorporating asecond embodiment of the invention;

FIG. 8 is a block diagram of a sigma-delta ADC circuit incorporating thesecond embodiment of the invention;

FIG. 9 is a flow chart illustrating the steps of the method of theinvention using fixed interpolation followed by variable decimation;

FIG. 10 is a block diagram of ADC circuit incorporating a thirdembodiment of the invention; and

FIG. 11 is a graph illustrating the relationship between the four-bitcodes and the corresponding sampling frequency in the circuit of FIG.10.

DETAILED DESCRIPTION

For purposes of illustration only, and not to limit generality, thepresent invention will now be explained with reference to specific datarates, interpolation (or more generally sample rate increase) ratios,decimation ratios, and clock frequencies of operation. One skilled inthe art will recognize that the present invention is not limited to thespecific embodiments disclosed, and can be more generally applied toother circuits and methods having different operating parameters thanthose illustrated.

FIG. 2 is a block diagram broadly illustrating a first embodiment of theinvention. The overall purpose of circuit 10 is to receive an analogsignal on line 12 at any frequency within a predetermined working rangeof the system, convert this signal to a digital data stream, increasethe sample rate of the digital data stream and then decimate this higherrate digital data stream so that the data presented on line 32 is at adesired sampling rate. The first embodiment uses variable interpolationfollowed by fixed decimation. In other words, circuit 10 receives, fromanalog to digital converter 11, digital data at a fixed, predetermineddata rate and converts this data to a digital data stream at anotherdata rate. The other data rate may or may not be the same as the datarate output by analog to digital converter 11 and may be at a fixed orvariable rate. The digital data stream on line 13 output by analog todigital converter 11 may be of any width. ADC 11 may be any well-knowntype of analog to digital converter.

In the circuit illustrated in FIG. 2, the analog signal on line 12 isconverted to a digital data stream on line 13 by ADC 11. The digitaldata stream on line 13 typically has a constant sample rate. Theconstant sample rate digital data stream on line 13 is filtered by lowpass filter 16 to remove out of band noise that results from the analogto digital conversion process. The filtered digital data stream on line17 is then sent to interpolator 18. Interpolator 18 increases the samplerate of the digital data stream (that is, converts the digital datastream into a higher sample rate digital data stream) on line 17 byusing a sample and hold technique that repeats the digital sample for aspecified number of clock cycles in a manner well-known to those skilledin the art. One skilled in the art will appreciate that other techniquesmay be used for increasing the sample rate of the data stream on line17, such as interpolation techniques that insert zeroes between datasamples. The purpose of interpolator 18 is to increase the sample rateof the digital data stream on line 17 to create a so-called oversampledsignal. It is to be appreciated that analog to digital converter 11 maybe an oversampling type converter itself, thus reducing the ratio bywhich interpolator 18 must increase the sample rate. However, ADC 11 maybe any type of analog to digital converter whose output sample rate isthen increased by interpolator 18.

The interpolation ratio (i.e., the ratio by which the sample rate of thedigital data on line 17 is increased by interpolator 18 is controlled bya sigma-delta modulator 20.

A higher sample rate digital data stream on line 19 is then sent to adigital filter 26 which removes any images of the original digitalsignal as a result of the interpolation process. The filtered digitaldata stream on line 28 is then sent to a decimation block 30 thatdecimates the digital data stream on line 28 by a fixed decimation ratioto produce the digital data stream on line 32 having a sample rateselected by a sampling frequency select signal 24. Although filter 26and decimation block 30 have been illustrated as separate circuitelements for illustrative purposes, one skilled in the art willappreciate that these functions may be performed by a single computationelement, such as an FIR or IIR filter in a well known manner.

The sigma-delta modulator 20 produces digital data at the frequency ofclock 22, the data controlling the interpolation of interpolator 18. Aswill be explained in more detail hereinafter, the sigma-delta modulator20 sigma-delta modulates a signal 24 representative of the desiredoutput sample rate of the digital data stream on line 32. An examplewill serve to illustrate this function. Assume that the data rate ofdigital data stream on line 13 is 3.072 mHz. Assume the frequency ofclock 22 is 3.072 mHz. If the desired data rate of the data stream online 32 is 48 kHz, signal 24 is therefore a multi-bit digital numberrepresentative of a sampling rate of 48 kHz where the number of bits inthe digital number control the precision with which the data rate of thedata stream on line 14 can be specified. This digital number issigma-delta modulated by the sigma-delta modulator 20 and used tocontrol interpolator 18 to increase the sample rate of the digital datastream on line 17 by a factor of six. Interpolator 18 increases thisdata rate to 18.432 mHz by interpolating the data by a factor of six.The resulting 18.432 mHz data is then decimated, after filtering byfilter 26, by a factor of 384 (decimator 30 having a decimation ratio of384) and the digital data stream emerging on line 32 is therefore at, onaverage, a 48 kHz data rate.

Sigma-delta modulator 20 is preferably an n-th order m-bit sigma-deltamodulator. The higher the order of the sigma-delta modulator, the betterthe noise shaped characteristics of the output signal on line 23. Theoutput signal on line 23 of sigma-delta modulator 20 is chosen to bem-bits (where m≧1 n and is more than one bit in a preferred embodiment)because, as the number of bits which control interpolator 18 isincreased, the clock rate necessary to operate sigma-delta modulator 20can be reduced. However, it is to be appreciated that the invention isnot so limited. Sigma-delta modulator 20 could also be a one bitmodulator if the clock frequency used to run the modulator isappropriately increased.

A key feature of the present invention is that the temporal spacing ofthe sampling points is controlled by the n-th order m-bit sigma-deltamodulator such that any errors (i.e., noise on the sampling points)produced by this nonuniform sampling are shaped in the frequency domain.That is, the digital signal produced by the interpolation/decimationprocess of the present invention is temporally noise-shaped. As iswell-known in the field of sigma-delta systems, this error produced bynoise resulting from the nonuniform sampling can be removed byconventional digital filtering techniques.

Several other advantages are also obtained. By appropriate choice of therate at which the sigma-delta spaced sampling points are generated andthe number of bits used in controlling the spacing of these samplingpoints, the signal-to-noise ratio of the digital data stream on line 32can be controlled. Further degrees of freedom are available by varyingthe order of the sigma-delta modulator used to control the samplingpoints. In another aspect of the invention, the degree of filtering usedon the digital data stream on line 19 can also be varied to vary thesignal-to-noise ratio as well.

FIG. 3 illustrates a more detailed embodiment of the ADC of FIG. 2. Inthe circuit 100 of FIG. 3, the analog signal on line 12 is convertedinto an oversampled constant rate digital data stream on line 42 byanalog to digital converter 30. Analog to digital converter 30 ispreferably a sigma-delta ADC because this results in the digital datastream on line 42 being already oversampled, thus reducing the factor bywhich the data stream on line 42 must have its sampling rate increasedbefore decimation. In one embodiment, the n-bit wide digital data streamon line 42 has a constant data rate of 3.072 mHz. The constant ratedigital data stream on line 42 is filtered by low pass filter 44 toremove out of band noise and sigma-delta noise that result from theanalog to digital conversion process carried out by ADC 30. The filtereddigital data stream on line 46 is then sent to interpolator 48.Interpolator 48 increases the sample rate of the digital data stream online 46 by using a sample and hold technique or an interpolationtechnique under control of sigma-delta modulator 40. The use of a sampleand hold technique is advantageous because it automatically compensatesfor the energy lost in creating the images of the original signal due tothe interpolation process. The higher rate digital data stream on line50 is then sent to low-pass filter 52 that removes images andsigma-delta noise from the digital data stream on line 50 that may bepresent as a result of the interpolation process. In one embodiment,digital filter 52 is a sinc 96³ -type filter. Filter 52 could, however,by any type of IIR or FIR filter.

The filtered digital data stream on line 54 is then sent to a decimationblock 56 that decimates the digital data stream on line 54 by a fixeddecimation ratio (96 in the illustrated embodiment). The decimateddigital data stream on line 58 is then filtered by low pass filter 60 toremove images and sigma-delta noise as a result of the nonuniformsampling. The filtered digital data stream on line 62 is then sent to adecimation block 64 that decimates the digital data stream on line 62 bya fixed decimation ratio (4 in the illustrated embodiment) to providethe digital data stream on line 66 at the data rate selected by a 20 bitsampling frequency selection number 43.

It is to be noted that digital data streams on lines 42, 46, 50, 54, 58,and 62 are indicated as being n-bits wide in FIG. 3. N may be any numberof bits and is typically chosen to be the widest bit stream commensuratewith the signal-to-noise ratio requirements of the particularapplication. Furthermore, the digital data streams may be differentwidths on each of the lines.

The n-th order m-bit sigma-delta modulator 40 provides a four-bit numberon line 41 that controls interpolator 48 to produce the digital datastream on line 50. In one embodiment, sigma-delta modulator 40 is afourth order four-bit modulator. Sigma-delta modulator 40 is alsoclocked using a 3.072 mHz clock.

In one embodiment, a twenty-bit frequency selection number 42 is inputinto sigma-delta modulator 40. Frequency selection number 42 ranges from-2¹⁹ to +2¹⁹. This twenty-bit number controls the precision with whichthe four-bit number output by sigma-delta modulator 40 represents thedesired sampling rate of the output digital data stream on line 66.Sigma delta modulator 40 modulates the twenty-bit number to producesigma-delta modulated four-bit codes that control interpolator 48. Thefirst bit of the code is a sign bit. The remaining three bits producecodes that control the interpolation ratio (i.e., the factor by whichthe sample rate of the digital data stream on line 46 is increased)provided by interpolator 48 to effectively convert the sample rate ofthe data stream.

Table 1 illustrates the relationship among the four-bit codes that areproduced by sigma-delta modulator 20, the ratio by which the sample rateof the digital data stream on line 46 is increased, and the samplingfrequency that the four-bit code corresponds to when modulator 20 isclocked using a 3.072 mHz clock. Some examples will illustrate theoperation of the system.

                  TABLE 1    ______________________________________              SAMPLE RATE              INCREASE FACTOR                            CORRESPONDING              ALLOW P CLOCKS                            TO SAMPLING    4 BIT CODE              TO PASS THROUGH                            FREQUENCY OF (kHz)    ______________________________________    +4        8             64    +3        7             56    +2        6             48    +1        5             40     0        4             32    -1        3             24    -2        2             16    -3        1              8    -4        0             DC    ______________________________________

Assume, for purposes of illustration, that the sample rate of thedigital data stream on line 42 is an oversampled data stream having aconstant sample rate of 3.072 mHz. Assume that the desired sample rateof the digital data stream on line 66 is 48 kHz. To produce the digitaldata stream on line 66 at 48 kHz, the digital data stream on line 62must have a sample rate of 192 kHz and the digital data stream on line50 must have a sample rate of 18.432 mHz. Therefore, twenty-bitfrequency selection number 43 is selected such that upon sigma-deltamodulation by the fourth order four-bit sigma-delta modulator 20, thefour-bit codes generated will be, on average, a +2 code, although otherfour-bit codes will be produced but with a lower frequency ofoccurrence.

Interpolator 48 uses a sample and hold technique under control ofsigma-delta modulator 40 to increase the sample rate of the digital datastream on line 46. The use of a sample and hold technique isadvantageous because it automatically compensates for the energy lost increating the images of the original signal due to the interpolationprocess.

A key point to remember is that the +2 code is the resulting average ofall codes produced by sigma-delta modulator 40 upon sigma-deltamodulation of twenty-bit frequency selection number 42. A +2 code is notproduced every time sigma-delta modulator 40 is clocked even though thesample rate of the digital data stream on line 42 and the sample rate ofthe digital data stream on line 66 are related to each other by aninteger multiple. Even if the sample rates were related to each other byan integer multiple, any errors, no matter how small, that result in atemporal displacement between the sample points in the digital datastream on line 42 and the sample points in the rate-converted digitaldata stream on line 52 would increase the signal-to-noise ratio to apoint where the analog to digital conversion process would not beacceptable. In the present invention, the time base (i.e., the temporalspacing between samples) is sigma-delta modulated so that the errors dueto temporal displacement between the digital data stream on line 42 andthe rate-converted digital data stream on line 50 that cause noise arepushed into a higher frequency range. This noise is then removed byconventional filtering techniques such as in digital filters 52 and 60.

As shown in Table 1, the +2 code (on average) directs interpolator 48 toincrease the sample rate of the digital data stream on line 46 by afactor of six. Interpolator 48 uses a sample and hold technique undercontrol of sigma-delta modulator 40 to increase the sample rate of thedigital data stream on line 46. The use of a sample and hold techniqueis advantageous because it automatically compensates for the energy lostin creating the images of the original signal due to the interpolationprocess. Alternatively, interpolator 48 may increase the sample rate byinterpolation using a zero fill technique to insert six zeros betweenevery sample of the digital data stream on line 46. Inserting zeros intothe digital data stream on line 46 will reduce the gain of the originalsignals because of dilution of the signal. The higher sample ratedigital data stream on line 50 has a sample rate of, on average, 18.432mHz. Upon decimation by decimator circuit 56 and decimator circuit 64,the digital data stream on line 66 emerges with a sample rate of, onaverage, 48 kHz.

In another example, assume that the desired sample rate of the digitaldata stream on line 66 is 4 kHz. To produce the digital data stream online 66 at 4 kHz, the digital data stream on line 62 must have a samplerate of 16 kHz and the digital data stream on line 50 must have a samplerate of 1.536 mHz. Therefore, twenty-bit frequency selection number 43is selected such that sigma-delta modulator 40 produces, on average, anequal number of -3 and -4 codes, although other four-bit codes will beproduced, but with a lower frequency of occurrence. As shown in Table 1,the -3 code directs interpolator 48 not to increase the sample rate(because the sample rate increase factor is 1). This corresponds to asampling frequency of 8 kHz for the clock frequencies and interpolationratios illustrated.

The -4 code controls interpolator 48 to increase the sample rate of thedigital data stream by a factor of zero. That is, interpolator 48, inresponse to a -4 code, produces no output, thus effectively decimatingthe digital data stream on line 46.

At the illustrated interpolation ratios and clock frequencies, the -3code represents a sampling frequency of 8 kHz and the -4 code representsa sampling frequency of DC (i.e., no signal). Therefore, on average ofmany samples, the -3 and -4 four-bit codes represent a samplingfrequency of 4 kHz. Thus, on average of many samples, after decimationby decimator 56 and decimator 64, the data rate of the digital data online 66 will be, on average, 4 kHz.

One skilled in the art will appreciate that any sampling frequencieswithin the 0 to 64 kHz range may be produced by varying the ratio offour-bit codes produced by sigma-delta modulator 40. For example, toobtain a sampling frequency between 56 kHz and 64 kHz, the appropriateratio of +3 and +4 codes would be output by sigma-delta modulator 40 asa function of twenty-bit number 43. One skilled in the art will alsoappreciate that any sample rate within the working range of the systemcan be produced through the appropriate combination of four-bit codes.

Although a four-bit sigma-delta modulator has been illustrated, theinvention is not so limited. For example, a sigma-delta modulator thatoutputs fewer bits can be used if the modulator is clocked at a fasterrate. In the same manner, a sigma-delta modulator that outputs a largernumber of bits can be used and the modulator can then be clocked at alower rate. One skilled in the art will appreciate that the number ofbits used and the clock rate used are a function of the desired noiseshaping and signal-to-noise ratio and may be traded off depending uponthe requirements of a particular application.

One skilled in the art will appreciate that, in the circuit of FIG. 3,both the magnitude and the temporal spacing of the digital samples aresigma-delta encoded by ADC 30 and sigma-delta modulator 40,respectively.

One of the advantages of sigma-delta modulation of the time base is thatthe jitter or time variation produced on the sampling time (or samplinginterval) due to the fact that interpolator 48 (under control ofsigma-delta modulator 20) produces output samples at time intervals thatmay not correspond exactly to the specified output sampling frequency (0kHz to 64 kHz in the illustrated embodiment) is varied by thesigma-delta modulator so that any errors that result from the noise orjitter around the sampling point have a sigma-delta noise characteristicthat can be removed by conventional filtering techniques, as forexample, by filter 26 or 52.

FIG. 4 is a block diagram of an alternative system for determiningfrequency selection number 43. In FIG. 4, a memory 70 (which may be RAMor ROM, for example) is used to store a look up table containingtwenty-bit numbers and the sampling frequency to which they correspond.In response to a frequency select signal from a user or an externalsource, decoder 72 selects the twenty-bit number from memory 70 mostclosely corresponding to the desired sampling frequency specified by thefrequency select signal. The twenty-bit number is then be output on bus74 to sigma-delta modulator 40.

FIG. 5 illustrates another embodiment of the invention in which adigital phase locked loop 200 incorporating sigma-delta modulator 20 or40 is added to the circuit of FIGS. 2 or 3 to allow the analog todigital converter to operate at and lock to an external clock signalsuch as an off-chip clock signal. In circuit 200, an external clocksource on line 80 is applied to a frequency counter 82 that produces asignal representative of the period of external frequency source on line80. In addition, the external clock on line 80 is applied to phasedetector 84 that produces a signal proportional to the phase differencebetween the external clock on line 80 and a signal on line 86 to bedescribed in more detail hereinafter. The output of phase detector 84 isfiltered by differentiating filter 88 and summed in summer 90 with thesignal representative of the period of the external clock source on line80 from the frequency counter 82. The output of summer 90 is fed into anintegrating filter 92 that functions as a low-pass filter. The output ofintegrating filter 92 is then sent to a circuit 94 that converts theperiod to a frequency by performing a 1/period function and providingany appropriate scaling. The signal from circuit 94 is then sent tosigma-delta modulator 40. The four-bit code from sigma-delta modulator40 is used to control interpolator 18 or interpolator 48 in the samemanner as described in connection with the embodiment of FIGS. 2 and 3,respectively.

The four-bit code is also fed into a clock generation circuit 98 thateffectively produces an output clock at 384 times greater than thesignal on line 80. Circuit 118 performs this function by suppressing acertain number of 24.576 mHz clock cycles in response to the four-bitcode from sigma-delta modulator 40. The following examples will serve toillustrate. Assume sigma-delta modulator 40 is clocked by a 3.072 mHzclock. For every 3.072 mHz clock, there are eight 24.576 mHz clocksapplied to circuit 98. In accordance with Table 1, circuit 118suppresses a number of 24.576 mHz clocks as a function of the four-bitcode output by sigma-delta modulator 40. For example, if the externalfrequency source on line 80 is 48 kHz, then sigma-delta modulator 40outputs, on average, a +2 code. The +2 code directs circuit 98 to allowsix out of every eight 24.576 mHz clocks to pass through. Stated anotherway, circuit 98 suppresses two out of every eight 24.576 mHz clocks inresponse to a +2 code.

If the external clock frequency source is 4 kHz, then sigma-deltamodulator 40 outputs, on average, an equal number of -3 and -4 codes.The -3 code directs circuit 98 to allow one out of every eight 24.576mHz clocks to pass through (i.e., circuit 98 suppresses seven out ofevery eight 24.576 mHz clocks in response to a -3 code). The -4 codedirects circuit 98 to allow no 24.576 mHz clocks to pass through (i.e.,circuit 98 suppresses eight out of every eight 24.576 mHz clocks inresponse to a -4 code). On average, therefore, one out of every sixteen24.576 mHz clocks will pass through suppressor circuit 118 in responseto an average of -3 and -4 codes.

If, however, the same clocks are suppressed for each four-bit code fromsigma-delta modulator 40, then unwanted tones may appear in the outputdata stream on line 101. Therefore, circuit 98 also performs theadditional function of randomly suppressing clock cycles in order tosuppress unwanted tones in the output data stream on line 101.Randomizing ensures that pulses in each of the eight positions (recallthat there are eight 24.576 mHz clock pulses for each 3.072 mHz clockpulse controlling sigma-delta modulator 78) are suppressed equally, onaverage. This may be accomplished by providing a latch for each bitposition that is set whenever the pulse in that position is suppressed.Pulses in that position are not suppressed again until all latchescorresponding to all the positions have been set, at which time thelatches are cleared and the sequence of suppression is repeated. Thisreduces tones that result from the clock pulse suppressor. Clockrandomizer/suppressor circuits are well-known in the art. One example ofsuch a circuit may be found in Phase Lock Loops, Theory, Design, andApplications by Dr. Roland E. Best, published by McGraw-Hill BookCompany, © 1984. Clock randomizer/suppressor circuit 98 outputs a clocksignal on line 101 that is sent through divider 102 having a dividerratio of 4 and a divider 104 having a divider ratio of 4 that reduce thesuppressed and randomized 24.576 mHz clock output by clockrandomizer/suppressor circuit 98 to the frequency of the external clockon line 80. Circuits 102 and 104 may be counters.

For the examples just discussed above, if the external clock on line 80is 48 kHz, then the signal on line 101 is approximately 18.432 mHz. Whendecimated by 96 and then 4, the signal on line 86 is 48 kHz. If theexternal clock on line 80 is 4 kHz, then the signal on line 101 isapproximately 1.536 mHz. When decimated by 96 and then 4, the signal online 86 is 4 kHz.

Circuit 94, sigma-delta modulator 40, and clock randomizer/suppressorcircuit 98 together form a digitally-controlled oscillator.

This particular embodiment of the present invention thus allows an ADCto, after converting an analog signal to digital data at a constant datarate, lock to an externally supplied clock source to allow operation ofthe ADC at a clock frequency that is not necessarily the same as or evenan integer or rational relationship with the master clock controllingthe ADC.

The embodiment of the invention illustrated in FIGS. 2-4 may becharacterized as using variable interpolation followed by fixeddecimation. That is, the digital data stream on line 13 or 42 isvariably interpolated under control of sigma-delta modulator 20 or 40,respectively, to variably increase the sample rate. This higher samplerate digital signal is then decimated by a fixed ratio to provide thedigital data stream on line 32 or 66 at another sample rate.

Reference is now made to FIG. 6 which is a flow chart illustrating afirst embodiment of the method of the present invention. FIG. 6illustrates the method of variable interpolation followed by fixeddecimation.

In FIG. 6, the method begins by receiving an analog signal in step 202.From step 202, the method proceeds to step 204 in which the analogsignal is converted into digital data. The digital data is typically ata constant data rate. From step 204, the method proceeds to step 206 inwhich a sampling frequency select signal representative of the desiredoutput sample rate is received. From step 206, the method proceeds tostep 208 in which the frequency select signal is sigma-delta modulated.From step 208, the method proceeds to step 210 in which the digital datais interpolated by a ratio determined by the sigma-delta modulatedfrequency select signal to increase the sample rate of the digital data.From step 210, the method proceeds to step 212 in which the interpolateddigital data is decimated by a fixed ratio to provide the output digitaldata at the desired sample rate. From step 212, the method proceeds tostep 214 in which the digital signal is output.

FIG. 7 is a block diagram broadly illustrating a second embodiment ofthe invention. As with the first embodiment illustrated in FIGS. 2-3,the overall purpose of circuit 250 is to receive an analog signal online 12 at any frequency within a predetermined working range of thesystem, convert this signal to a digital data stream, increase thesample rate of the digital data stream and then decimate this higherrate digital data stream so that the data presented on line 14 is at adesired sampling rate. The second embodiment uses fixed interpolationfollowed by variable decimation. ADC 11 is FIG. 7 may be the same asthat illustrated in FIGS. 2-3.

In the circuit illustrated in FIG. 7, the analog signal on line 12 isconverted to a digital data stream on line 13 by ADC 11. The digitaldata stream on line 13 typically has a constant sample rate. Aninterpolator 252 receives the digital data stream on line 13 at thepredetermined data rate. Interpolator 253 increases the sample rate ofthe digital data stream (that is, converts the digital data stream intoa higher sample rate digital data stream) on line 254 by, for example,inserting zeros between data samples, in a manner well-known to thoseskilled in the art. One skilled in the art will appreciate that othertechniques may be used for increasing the sample rate of the data streamon line 13, such as sample and hold techniques. As noted previously, thepurpose of interpolator 252 is to increase the sample rate of thedigital data stream on line 13 to create a so-called oversampled signal.It is to be appreciated that analog to digital converter 11 may be anoversampling type converter itself, thus reducing the ratio by whichinterpolator 252 must increase the sample rate. However, ADC 11 may byany type of analog to digital converter whose output sample rate is thenincreased by interpolator 252.

A higher sample rate digital data stream on line 254 is then sent to adigital filter 256 which removes any images of the original digitalsignal as a result of the interpolation process. The filtered digitaldata stream on line 258 is then sent to a decimation block 260 thatdecimates the digital data stream on line 258 under control of clockrandomizer/suppressor circuit 262 which is in turn controlled by thesigma-delta modulator 20 as will be explained in more detailhereinafter. Although filter 256 and decimation block 260 have beenillustrated as separate circuit elements for illustrative purposes, oneskilled in the art will appreciate that these functions may be performedby a single computational element, such as an FIR or IIR filter in awell-known manner. Sigma-delta modulator 20 operates in the same manneras described in connection with the embodiment of FIGS. 2-3.

The m-bit code output signal on line 23 from sigma-delta modulator 20 isfed into a clock randomizer/suppressor circuit 98 that effectivelyproduces an output clock at 384 times greater than the data rate of thedigital signal on line 13. In one embodiment, clock 25 is a 24.576 mHzclock. Circuit 98 operates in the same manner as already described inconnection with FIG. 5. The following explanation is provided foradditional clarification.

Circuit 98 provides a clock on line 264 by suppressing a certain numberof cycles of clocks from clock 25 in response to the m-bit code on line23 from sigma-delta modulator 20. If, however, the same clocks in thesame temporal positions are suppressed for each multi-bit code fromsigma-delta modulator 20, then unwanted tones may appear in the outputdata stream on line 264. Therefore, circuit 98 also performs theadditional function of randomly suppressing clock cycles in order toprevent unwanted tones in the output data stream on line 264. Asdescribed previously, clock suppressor and randomizer circuits arewell-known in the art. One example of such a circuit may be found inPhase Locked Loops by Dr. Roland E. Best, published by McGraw-Hill BookCompany, © 1984. Clock suppressor/randomizer circuit 98 is needed in thesecond embodiment to produce a clock on line 25 having a clock frequencythat is 384 times the data rate specified by sampling frequencyselection number 24 since sigma-delta modulator 20 is clocked using afixed clock frequency and a variable clock frequency is needed tovariably decimate the data on line 258. Clock randomizer/suppressorcircuit 98 outputs a clock signal on line 265 that controls thedecimation of decimator 260.

In one embodiment, the digital data stream on line 13 has a data rate of3.072 mHz. This n-bit wide digital data stream on line 13 is fed intointerpolator 252. Interpolator 252 increases the sample rate of thedigital data stream on line 13 by a factor of eight using, for example,a zero fill technique that inserts zeros between the digital samples. Asis well-known, the parameters of filter 256 can be adjusted tocompensate for any loss of gain. A higher sample rate signal on line 254output by interpolator 252 (now at 24.576 mHz) is then fed into digitalfilter 256.

As stated previously, other techniques, such as sample and holdtechniques, may be used to increase the sampling rate in place ofinterpolator 252.

In the more detailed embodiment illustrated in FIG. 8, digital filter256 is a filter that is designed to have zeros at the image frequenciesof the digital data stream on line 254. The filtered higher sample ratedigital data on line 266 is then sent to decimator 269 that decreasesthe sample rate by a variable ratio so that the digital data on line271, after filtering by filter 264 and decimation by a fixed ratio ofninety-six in decimator 268 and a fixed ratio of four in decimator 276,emerges on line 278 with a sample rate specified by frequency selectionnumber 280. Filter 264 is a sinc 93³ -type filter but could be any typeof FIR or IIR filter. In addition, filter 264 and decimator 269 could becombined into a single element as noted in connection with FIG. 7.

Sigma-delta modulator 20 produces a four-bit code representative offrequency selection number 280 at a constant rate of 3.072 mHz inresponse to clock 22. However, decimator 269 must produce the digitaldata stream on line 271 having sample rates of, for example, between1.536 mHz and 24.576 mHz depending upon the desired sample rate of theoutput data stream. Therefore, clock randomizer/suppressor circuit 98 isneeded to produce a variable rate clock on line 25 or 265 to variabledecimate the data on line 266.

Table 1 illustrates the relationship among the four-bit codes that areproduced by sigma-delta modulator 20, the number of clocks that areallowed to pass through randomizer/suppressor circuit 98, and the outputsample rate that the four-bit code corresponds to when modulator 20 isclocked using a 3.072 mHz clock and when clock randomizer/suppressorcircuit 98 is clocked using a 24.576 mHz clock. Some examples willillustrate the operation of the second embodiment.

Assume, for purposes of illustration, that the sample rate of thedigital data stream on line 13 is an oversampled data stream having aconstant sample rate of 3.072 mHz. Assume that the desired sample rateof the digital data stream on line 278 is 48 kHz. Interpolator 252increases the data rate of the digital data stream on line 13 by afactor of eight to 24.576 mHz. To produce the digital data stream online 278 at 48 kHz, the digital data stream on line 274 must have asample rate of 192 kHz and the digital data stream on line 266 must havea sample rate 18.432 mHz. Therefore, twenty-bit frequency selectionnumber 280 is selected such that upon sigma-delta modulation by thefourth order four-bit sigma-delta modulator 20, the four bit codesgenerated will be, on average, a +2 code although other four bit codeswill be produced but with a lower frequency of occurrence.

The +2 code is then applied to clock randomizer/suppressor circuit 98.For every 3.072 mHz clock applied to sigma-delta modulator 20, there areeight 24.576 mHz clocks applied to clock randomizer/suppressor circuit98. In accordance with Table 1, circuit 98 suppresses a number of 24.576mHz clocks as a function of the four-bit code output by sigma-deltamodulator 20. The +2 code directs circuit 98 to allow six out of everyeight 24.576 mHz clocks to pass through. Stated another way, circuit 98suppresses two out of every eight 24.576 mHz clocks in response to a +2code. As discussed in conjunction with the embodiment of FIG. 7, circuit98 randomly suppresses the specified number of clock cycles in order toprevent unwanted tones in the output data stream on line 26.

In another example, assume that the desired sample rate of the digitaldata stream on line 278 is 4 kHz. Interpolator 252 increases the datarate of the digital data stream on line 13 by a factor of eight to24.576 mHz. To produce the digital data stream on line 278 at 4 kHz, thedigital data stream on line 274 must have a sample rate of 16 kHz andthe digital data stream on line 266 must have a sample rate of 1.536mHz. Therefore, twenty-bit frequency selection number 280 is selectedsuch that sigma-delta modulator 20 produces, on average, an equal numberof -3 and -4 codes although other four-bit codes will be produced, butwith a lower frequency of occurrence. That is, occasionally, -2, -1, andeven less frequently, +1, +2 codes will be produced. As shown in Table1, the -3 code directs circuit 98 to allow one out of every eight 24.576mHz clocks to pass through (i.e., circuit 98 suppresses seven out ofevery eight 24.576 mHz clocks in response to a -3 code). The -4 codedirects circuit 98 to allow no 24.576 mHz clocks to pass through (i.e.,circuit 98 suppresses eight out of every eight 24.576 mHz clocks inresponse to a -4 code). On average, therefore, one out of every sixteen24.576 mHz clocks will pass through suppressor circuit 98 in response toan average of -3 and -4 codes.

At the illustrated interpolation ratios and clock frequencies, the -3code represents a sampling frequency of 8 kHz and the -4 code representsa sampling frequency of DC (i.e., no signal). Therefore, on average ofmany samples, the -3 and -4 four-bit codes represent a samplingfrequency of 4 kHz times 384 to provide a clock on line 265 or 25 at (4kHz (384)=1.536 mHz.

It is to be noted that digital data streams 13, 254, 266, 271, 273, 270,and 274 are indicated as being N-bits wide in FIGS. 8 and 10. N may beany number of bits and is typically chosen to be the widest bit streamcommensurate with the signal-to-noise ratio requirements of theparticular application.

The embodiment of the invention illustrated in FIGS. 7-8 may becharacterized as using fixed interpolation followed by variabledecimation. That is, the digital data stream output by analog to digitalconverter 11 or 30 is interpolated by a fixed ratio to increase thesample rate. This higher sample rate digital signal is then variablydecimated under control of sigma-delta modulator 20 and clockrandomizer/suppressor circuit 98 to provide the digital data stream online 32 or 278 at a sample rate within the working range of the system.

The second embodiment can generate sampling frequencies within the 0 to64 kHz range by varying the ratio of four-bit codes in the same manneras the first embodiment. The second embodiment provides all of thefeatures and advantages discussed in connection with the firstembodiment. The second embodiment can also be used with the circuitsillustrated in FIGS. 4 and 5 in the same manner.

Reference is now made in FIG. 9 which is a flow chart illustrating asecond embodiment of the method of the present invention. FIG. 9illustrates the method of the fixed interpolation followed by variabledecimation.

In FIG. 9, the method begins by receiving an analog signal in step 300.From step 300, the method proceeds to step 302 in which the receivedanalog signal is converted into digital data. The digital data istypically at a constant data rate. From step 302, the method proceeds tostep 304 in which the digital data is interpolated by a fixed ratio toincrease the sample rate of the digital data. From step 304, the methodproceeds to step 306 in which a sampling frequency select signalrepresentative of the desired output sample rate is received. From step306, the method proceeds to step 308 in which the sampling frequencyselect signal is sigma-delta modulated. From step 308, the methodproceeds to step 310 in which the interpolated digital data is decimatedunder control of the sigma-delta modulated frequency select signal by aratio determined by the sigma-delta modulated frequency select signal toprovide digital data at the desired output sample rate. From step 310,the method proceeds to step 312 in which the digital signal is output.

Reference is now made to FIG. 10 which figure illustrates a thirdembodiment of the present invention. In particular, FIG. 10 modifies thecircuit of FIG. 8 by eliminating the clock randomizer/suppressorcircuit. In all other respects, the components and operation of thecircuit of FIG. 10 are the same as those illustrated in FIG. 8. Thecircuit of FIG. 10 operates in accordance with the method illustrated inFIG. 9, namely, FIG. 10 performs a fixed interpolation of the digitaldata on line 13 followed by a variable decimation of the interpolateddata on line 254 provide digital data on line 266 such that afterdecimation by decimation block 268 and decimation block 276, dataemerges on line 278 at the data rate specified by sampling frequencyselect number 280.

Since the clock randomizer/suppressor circuit is eliminated, sigma-deltamodulator 20 produces a four-bit code that directly controls thedecimation ratio provided by filter 264.

Table 2 illustrates the relationship among the four-bit codes that areproduced by sigma-delta modulator 20, the intervals at which decimator269 produces an output, and the sampling frequency that the four-bitcode corresponds to when modulator 20 is clocked using a 3.072 mHzclock. For example, a -4 code controls decimator 269 to produce oneoutput for every sample on line 266 and a +3 code controls decimator 269to produce one output every eighth samples on line 266. Decimator 269operates in the same manner as the decimators discussed in connectionwith the first two embodiments.

                  TABLE 2    ______________________________________                             CORRESPONDING             PRODUCE AN OUTPUT                             TO SAMPLING    4 BIT CODE             EVERY P SAMPLES FREQUENCY OF (kHz)    ______________________________________    +5       10              4.8    +4       9               5.333    +3       8               6    +2       7               6.857    +1       6               8     0       5               9.6    -1       4               12    -2       3               16    -3       2               24    -4       1               48    -5       0               00    ______________________________________

FIG. 11 graphically illustrates the 1/n relationship between thefour-bit codes and the corresponding sampling frequency. One skilled inthe art will appreciate that the system is nonlinear in the sense ofmapping the four-bit codes to a corresponding sampling frequency onlybecause of the particular interpolation ratios, decimation ratios, anddata rates chosen. However, the system itself is linear and, byproviding an operation that corrects for the nonlinear mapping of thefour-bit codes to the corresponding sampling frequency, a linearlymapped system as in the first two embodiments previously described canbe provided. Alternatively, the interpolation ratios, decimation ratios,and data rates may be selected so that there is a linear relationshipbetween four-bit codes and corresponding sampling frequencies. Oneskilled in the art will also appreciate that the 1/n relationshipbetween four-bit codes and sampling frequency illustrated in FIG. 11 andTable 2 is meant to be exemplary only; other relationships are possible(for all embodiments of the invention) and are to be considered withinthe scope of the present invention.

The circuit illustrated in FIG. 10 can generate sampling frequencieswithin the 0 to 64 kHz range by varying the ratio of four-bit codes inthe same manner as discussed in conjunction with the first twoembodiments. The embodiment illustrated in FIG. 10 can also be used withthe circuits illustrated in FIGS. 5 and 6 in the same manner.

Although the mapping between four-bit codes and sampling frequency isnonlinear in the embodiment illustrated in FIG. 10, this embodiment doesprovide certain advantages. In the embodiment illustrated in FIGS. 7-8,a clock randomizer/suppressor circuit was used. The clockrandomizer/suppressor circuit can result in a system having a reducedsignal to noise ratio as compared to the embodiments of the inventionillustrated in FIGS. 2-3 and 10, since the clock randomizer/suppressorcircuit reprocesses the sigma-delta modulated clock signal generated bythe sigma-delta modulator and suppresses clock signals in a linearmanner. This may degrade the noise shaping provided by the sigma-deltamodulator. The circuit illustrated in FIG. 10 is advantageous in thatthe clock randomizer/suppressor circuit is eliminated and the circuitcan still provide a fixed interpolation followed by variable decimationmethod of operation. Thus, the circuit of FIG. 10 can provide fixedinterpolation followed by variable decimation with no degradation in thesignal to noise ratio.

Another significant advantage of all embodiments of the presentinvention is that the ADC does not have to be capable of interpolatingthe digital data up to the lowest common frequency between the digitaldata rate and the modulator clock frequency. This is due to thesigma-delta modulation of the sampling intervals. Unlike prior art ADCs,the sampling interval does not have to correspond exactly to a fixedrelationship between the digital data rate and the modulator clock.Since the sample rate is sigma-delta encoded in the present invention(i.e., temporally noise-shaped), the sample rate, on average, willrepresent the desired sample rate with the noise or jitter on thesampling points being pushed into the higher frequency ranges. Thepresent invention thus takes advantage of sigma-delta encoding of thetime base to avoid the need for interpolation to very high frequencies,which in the prior art, typically were in the gigahertz range. Anadditional benefit of this process is that on an integrated circuit, asignificant savings in chip area can be realized by the use of lowerinterpolation ratios.

Another important advantage of the present invention is that thesigma-delta modulator 20 or 40 used to control interpolation ordecimation can be clocked using a fixed clock frequency, allowingoptimization of the modulator operation at the fixed clock frequency.

Finally, by appropriate combination of sigma-delta control codes inappropriate percentages, an infinite number of sample rates for theoutput digital data stream can be provided. These sample rates do notneed to have any integer or rational relationship with the master clockused to run the ADC.

Although interpolation has been used herein to explain the method (andan interpolator as the apparatus) by which the digital data stream isconverted into a higher sample rate digital data stream, the presentinvention is not so limited. Any method or apparatus that converts thedigital data stream into a higher sample rate digital data stream may beused to practice the invention.

Interpolators and decimators useful in the present invention may beconstructed as shown in Introduction to Digital Signal Processing byJohn Proakis and Dimitris Manolakis, published by Macmillan PublishingCompany, © 1988.

Having thus described several particular embodiments of the invention,various alterations, modifications, and improvements will readily occurto those skilled in the art. For example, the present invention can beused in conjunction with any type of ADC or analog to digital conversionmethod and is not limited to sigma-delta ADCs. Such alterations,modifications, and improvements are intended to be part of thisdisclosure, and are intended to be within the spirit and scope of theinvention. Accordingly, the foregoing description is by way of exampleonly and is not intended as limiting. The invention is limited only asdefined in the following claims and the equivalents thereto.

What is claimed is:
 1. An analog to digital converter system,comprising:analog to digital conversion means for converting an analogsignal to a digital signal a first data rate; interpolation means,coupled to the analog to digital conversion means, for receiving thedigital signal having the first data rate and for supplying a digitalsignal having an increased data rate; decimation means, coupled to theinterpolation means, for decimating the digital signal having theincreased data rate to provide a digital signal having a second datarate; and modulator means, coupled to and controlling the decimationmeans, for providing a modulated output signal representative of thesecond data rate and for controlling the decimation means to provide thedigital signal having the second data rate.
 2. The analog to digitalconverter system of claim 1, wherein the modulator means comprises asigma-delta modulator.
 3. The analog to digital converter system ofclaim 2, wherein the modulated output signal is a multi-bit code.
 4. Theanalog to digital converter system of claim 2, wherein the sigma-deltamodulator is an n^(th) -order modulator where n is ≧ to
 1. 5. The analogto digital converter system of claim 2, wherein the sigma-deltamodulator modulates a sampling frequency select signal representative ofthe second data rate.
 6. The analog to digital converter system of claim5, further comprising a memory means for storing a plurality offrequency selection numbers representative of the second data rate andmeans for selecting one of the frequency selection numbers in responseto a selection signal and for providing the selected number to thesigma-delta modulator as the sampling frequency select signal.
 7. Theanalog to digital converter system of claim 5, wherein the interpolationmeans interpolates the digital signal having the first data rate by afixed ratio.
 8. The analog to digital converter system of claim 7,wherein the decimation means decimates the digital signal having theincreased data rate by a ratio determined by the sampling frequencyselect signal to provide the digital signal having the second data rate.9. The analog to digital converter system of claim 5, further comprisinga clock generator means for generating, in response to the modulatedoutput signal, a clock having a frequency representative of the seconddata rate.
 10. The analog to digital converter system of claim 2,further comprising:phase-locked loop means, coupled to the sigma-deltamodulator means, for receiving a signal representative of the seconddata rate, locking to the signal, and providing a control signal to thesigma-delta modulator means that controls the sigma-delta modulatormeans to provide the sigma-delta modulated output signal.
 11. The analogto digital converter system of claim 1, further comprising a filtermeans, coupled between the interpolation means and the decimation means,for filtering out noise and images of the digital signal having thefirst data rate.
 12. The analog to digital converter system of claim 1,wherein the analog to digital converter is a sigma-delta analog todigital converter.
 13. An analog to digital converter system,comprising:an analog to digital converter; an interpolator having aninput electrically coupled to an output of the analog to digitalconverter; a decimator having an input electrically coupled to an outputof the interpolator; and a modulator electrically coupled a controlinput of the decimator and providing a temporally noise-shaped controlsignal that controls the decimation ratio provided by the decimator. 14.The analog to digital converter system of claim 13, wherein the analogto digital converter is a sigma-delta analog to digital converter.
 15. Amethod of converting an analog signal to a digital signal, comprisingthe steps of:converting an analog signal to a digital signal having afirst data rate; modulating a control signal to provide a modulatedoutput signal representative of a second data rate; increasing the firstdata rate to provide a digital signal having an increased data rate; anddecimating the digital signal at the increased data rate in response tothe modulated output signal to provide a digital signal having a seconddata rate.
 16. The method of claim 15, wherein the step of modulating acontrol signal further comprises sigma-delta modulating the controlsignal.
 17. The method of claim 16, further comprising the step offiltering the digital signal having the increased data rate prior to thestep of decimating.
 18. The method of claim 17, wherein the step ofincreasing the first data rate includes increasing the data rate by afixed ratio.
 19. The method of claim 18, wherein the step of decimatingthe digital signal having the increased data rate includes decimatingthe digital signal having the increased data rate by a ratio determinedby the modulated output signal.
 20. The method of claim 15, wherein thestep of converting an analog signal to a digital signal includes thestep of sigma-delta modulating a magnitude of the analog signal.
 21. Amethod of converting an analog signal to a digital signal, comprisingthe steps of:converting an analog signal to a digital signal having afirst data rate; increasing the first data rate by a fixed ratio toprovide a digital signal having an increased data rate; and decimatingthe digital signal having the increased data rate by a variable ratio toprovide a temporally noise-shaped digital signal having a second datarate.
 22. The method of claim 21, wherein the step of converting ananalog signal to a digital signal includes the step of sigma-deltamodulating a magnitude of the analog signal.